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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
INTRODUCTION
S6B0708 is a single-chip LCD driver IC for liquid crystal dot-matrix graphic display systems. It incorporates 192 driver circuit for 64 common and 128 segment and 64 x 128-bit bit-map RAM. It is capable of interfacing with the microprocessor, accepting 8-bit parallel display data directly from it, and storing data in an one chip display data RAM. And it generates internal signals for using LCD driving independent of microprocessor clock.
FEATURES
* * * * * * * * * * * 64-channel common & 128-channel segment driver for dot matrix LCD On-chip display data RAM: 64 x 128 = 8192bits Display data is stored in display data RAM from MPU - RAM bit data: ON(1), OFF(0) Internal timing generator circuit for dynamic display 8-bit parallel bi-directional data bus Applicable LCD duty: 1/64 Power supply voltages: Power supply voltage range: 4.5 - 5.5V (VDD) LCD driving voltage range: 8.0 - 17.0V (VLCD = VDD-VEE) Wide operating temperature range: Ta = -30C - 85C High voltage CMOS process Gold bumped chip available
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
BLOCK DIAGRAM
C1 ... C32 S1 S2 ... S63 S64 S65 S66 ... S127 S128 C33...C64
...
...
...
...
VDD V0 V1 V2 V3 V4 V5 VEE VSS FS Display Timing Generator Circuit Page & Line Decoder Page & Line Decoder 64-Bit Data Latch 64-Bit Data Latch 32 Channel Common 64 Channel Segment Driver 64 Channel Segment Driver 32 Channel Common
32bit Shift Reg
32bit Shift Reg
SHL PCLK2
C CR R
Oscillator
Display Data RAM 64 X 64 = 4,096 Bits
Display Data RAM 64 X 64 = 4,096 Bits
Column Decoder
Column Decoder
ADC
RAM Address Register
RAM Address Register
Status Register
Instruction Decoder
Instruction Decoder
Status Register
I/O Buffer
I/O Register
I/O Buffer
4 CS1B RESETB E RS RW CS2B DB0 - DB7
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
PAD CONFIGURATION
218 219 Y S6B0708 (0, 0) X 250 1
86 85 54 53
Item Chip size Pad pitch Bumped pad size
Pad No. X 1 - 53 54 - 85 86 - 218 219 - 250 56 140 56 140 12590
Size Y 3630 90 (min.) 140 56 140 56 17 (typ.)
Unit m
Bumped pad height
All Pad
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
PAD CENTER COORDINA TES
Pad No. Pad Name X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Dummy Dummy Dummy VEE VEE VEE V5 V5 V5 V4 V4 V4 V3 V3 V3 V2 V2 V2 V1 V1 V1 V0 V0 V0 VDD VDD VDD VSS VSS VSS PCLK2 FS SHL ADC -6115 -6025 -5935 -5477 -5257 -5037 -4817 -4597 -4377 -4157 -3937 -3717 -3497 -3277 -3057 -2837 -2617 -2397 -2177 -1957 -1737 -1517 -1297 -1077 -857 -637 -417 -197 23 243 463 683 903 1123 Y -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 CS2B C CR R DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RS RW E CS1B RESETB Dummy Dummy C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Coordinate Pad No. Pad Name X 1343 1563 1783 2003 2175 2467 2759 3051 3343 3635 3927 4219 4559 4779 4999 5219 5439 6025 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 Y -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1600 -1386.5 -1296.5 -1206.5 -1116.5 -1026.5 -936.5 -846.5 -756.5 -666.5 -576.5 -486.5 -396.5 -306.5 -216.5 -126.5 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 Dummy Dummy S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 Coordinate Pad No. Pad Name X 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6115 6025 5715 5625 5535 5445 5355 5265 5175 5085 4995 4905 4815 4725 4635 Y -36.5 53.5 143.5 233.5 323.5 413.5 503.5 593.5 683.5 773.5 863.5 953.5 1043.5 1133.5 1223.5 1313.5 1403.5 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 Coordinate
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
Table 1. Pad Center Coordinates (Continued)
Pad No. Pad Name Coordinate X 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 4545 4455 4365 4275 4185 4095 4005 3915 3825 3735 3645 3555 3465 3375 3285 3195 3105 3015 2925 2835 2745 2655 2565 2475 2385 2295 2205 2115 2025 1935 1845 1755 1665 1575 Y 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 Pad No. Pad Name Coordinate X 1485 1395 1305 1215 1125 1035 945 855 765 675 585 495 405 315 225 135 45 -45 -135 -225 -315 -405 -495 -585 -675 -765 -855 -945 -1035 -1125 -1215 -1305 -1395 -1485 Y 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 Pad No. Pad Name Coordinate X -1575 -1665 -1755 -1845 -1935 -2025 -2115 -2205 -2295 -2385 -2475 -2565 -2655 -2745 -2835 -2925 -3015 -3105 -3195 -3285 -3375 -3465 -3555 -3645 -3735 -3825 -3915 -4005 -4095 -4185 -4275 -4365 Y 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
Table 1. Pad Center Coordinates (Continued)
Pad No. Pad Name Coordinate X 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 Dummy Dummy Dummy C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 -4455 -4545 -4635 -4725 -4815 -4905 -4995 -5085 -5175 -5265 -5355 -5445 -5535 -5625 -5715 -5935 -6025 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 Y 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1635 1403.5 1313.5 1223.5 1133.5 1043.5 953.5 863.5 773.5 683.5 593.5 503.5 413.5 323.5 233.5 143.5 53.5 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 Pad No. Pad Name Coordinate X -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 -6115 Y -36.5 -126.5 -216.5 -306.5 -396.5 -486.5 -576.5 -666.5 -756.5 -846.5 -936.5 -1026.5 -1116.5 -1206.5 -1296.5 -1386.5 Pad No. Pad Name Coordinate X Y
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
PAD DESCRIPTION
POWER SUPPLY Name VDD VSS VEE V0, V1 V2, V3 V4, V5 I/O Type Supply Supply Supply Supply Ground For LCD driver circuit LCD driver supply voltages The voltages must satisfy the following relationship VDD V0 V1 V2 V3 V4 V5 VEE Description Power supply. connect to MPU power supply pin VCC
OSCILLATOR Name C I/O Type O Description RC oscillator - Internal clock S6B0708 CR I R Rf CR Cf C
R
O - External clock
S6B0708 R Open CR External clock C Open
FS
I
Frequency selection When the frame frequency is 70Hz, the oscillation frequency should be as the following table.
FS H L Oscillation Frequency Fosc = 430kHz Fosc = 215kHz
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
MICROPROCESSOR INTERFACE Name CS1B CS2B RS I/O Type I I I Description First chip(S1 ~ S64) select input. Data input/output is enabled via E, RS, RW, and DB[0:7]when CS1B = Low. Second chip(S65 ~ S128) select input. Data input/output is enabled via E, RS, RW, and DB[0:7] when CS2B = Low. Register selection
RS H L Description The data in DB[7:0] is display data. The data in DB[7:0] is control data.
RW
I
Read or write
RW H L Description Data appears at DB[7:0] when E = high. Display data DB[7:0] can be written at falling edge of E.
E
Enable signal.
E H L Description Read data in DB[7:0] appears while E = high. Display data DB[7:0] is latched at falling edge of E.
DB0 - DB7
I/O
Data bus [0 - 7] Bi-directional data bus
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
RESET Name RESETB I/O Type I Description Reset input Chip is initialized when RESETB is low
LCD DRIVER OUTPUTS Name C1 - C64 S1 - S128 PCLK2 I/O Type O O I LCD driver common output LCD driver segment output Phase of internal shift clock (CLK2)
PCLK2 H L Phase of Internal Shift Clock (CLK2) Data shift at the rising edge of CLK2 Data shift at the falling edge of CLK2
Description
ADC
I
Address control signal of Y address counter.
ADC H L Segment Output Direction S1 S2 ..... S63 S65 S66 ..... S127 S128 S64 S63 ..... S2 S1 S128 S127..... S66 S65
SHL
I
Selection of data shift direction
SHL H L Data Shift Direction C1 C2 C3 ..... C62 C63 C64 C64 C63 C62 ..... C3 C2 C1
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
FUNCTIONAL DESCRIPTI N O
CHIP SELECT INPUT The S6B0708 has two chip select pins, CS1B and CS2B. It can interface with a microprocessor when these pins (CS1B or CS2B) are low. When both of these pins are set to high, DB0 to DB7 are at high impedance and RS, RW, and E inputs are disabled. CS1B pin controls the display status of S1 to S64, and CS2B does that of S65 to S128. When CS1B and CS2B are low at the same time, it is impossible to execute read operation. Therefore one of CS1B or CS2B should be set to low ((CS1B = H & CS2B = L) or (CS1B = L & CS2B = H)) in read operation. The RESETB signal is entered independent of the status of chip select. Table 2. Relationship Between Chip Select Pins and Read/Write Operation CS1B H L H L
( -:
CS2B H H L L
Read Operation CS1 X O X CS2 X X O -
W rite Operation CS1 X O X O CS2 X X O O
Not recommended, : Operation, X: No operation)
MICROPROCESSOR INTERFACE S6B0708 transfers 8-bit parallel in either direction between the controlling microprocessor and the S6B0708 through the 8-bit I/O buffer (DB0 to DB7). RS, RW and E identify the type of parallel data transfer to be made as shown below in Table 3. Table 3. Microprocessor Interface RS H H L L RW H L H L Read display data Write display data Status read Write to internal register (instruction) Description
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
BUSY FLAG Busy flag indicates whether S6B0708 is operating or not. When it is high, S6B0708 is in internal operation. When it is low, S6B0708 can accept the data or instruction. DB7 indicates busy flag of the S6B0708.
E
Busy Flag T B U S Y < 4 / fo s c
Figure 1. Busy Timing
DISPLAY TIMING GENER ATOR CIRCUIT This section explains how the timing generation circuit operates. * Signal generation to display start line counter and display data latch circuit. * The display clock (CLK2) generates a clock to the line counter. The display start line address of the display RAM is synchronized with the display clock. 128-bit display data is latched by the display data latch circuit in synchronization with the display clock and output to the segment LCD drive output pin. * LCD AC signal (M) generation.
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
DISPLAY DATA RAM (DD RAM) The display data RAM stores pixel data for the LCD. It is a 128-column x 64-row addressable array as shown in Table 4. The 64 rows are divided into 8 pages of 8 lines. Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The microprocessor reads data from and writes data to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written to RAM at the same time as the data is being displayed, without causing a LCD flicker.
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
1 1 1 1 1 1 1 0
0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0
0 1 0 0 0 1 0 0
1 0 0 0 0 0 1 0
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 LCD Panel
Display Data RAM
Figure 2. RAM to LCD Panel Data Transfer
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
Table 4. Display Data RAM
Page Address Line Address S1 000 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Segment Output (S1-S64) S2 *** S63 S64 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Data Bus Segment Output (S6-S128) S65 S66 S127 S128 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 000 Line Page Address Addres s
001
001
010
010
011
011
100
100
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
Table 4. Display Data RAM (Continued)
Page Address Line Address S1 101 40 41 42 43 44 45 46 47 110 48 49 50 51 52 53 54 55 111 56 57 58 59 60 61 62 63 ADC 1 0 0 63 1 62 62 1 63 0 S2 Segment Output (S1-S64) *** S63 S64 DB0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 0 63 1 62 62 1 63 0 S65 S66 Data Bus Segment Output (S6-S128) S127 S128 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 1 0 ADC 111 110 101 Line Address Page Address
Column Address Chip Select (CS1B)
Column Address Chip Select (CS2B)
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
MPU Signal RS RW E DB[7:0]
N D(N) D(N+1) D(N+2) D(N+3) D(N+4) D(N+5)
Internal Signal WR Input Buffer Column Address Page Address RAM
N N
Preset
D(N) N+1
D(N+1) N+2
D(N+2) N+3
D(N+3) N+4
D(N+4) N+5
N
Set page address => K
D(N)
D(N+1)
D(N+2)
D(N+3)
D(N+4)
Figure 3. Write Timing
MPU Signal RS RW E DB[7:0]
N Dummy D(N) D(N+1) D(N+2) D(N+3)
Internal Signal WR RD Output Buffer Column Address Page Address
Dummy N Preset K Set page address K D(N) N+1 D(N+1) N+2 D(N+2) N+3 D(N+3) N+4 D(N+4) N+5
Figure 4. Read Timing
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
DATA TRANSFER To match the timing of the display data RAM and registering to that of the controlling microprocessor, S6B0708 uses an internal data bus and bus buffer. When the microprocessor reads the contents of display data RAM, the data for the initial read cycle is first stored in the bus buffer (dummy read cycle). On the next read cycle, the data is read from the bus buffer onto the microprocessor bus. At the same time, the next block of data is transferred from RAM to the bus buffer. Otherwise, when the microprocessor write data to display data RAM, the data is written to RAM after the falling edge of "E". Therefore, it is necessary to check busy flag to write or read the next data. (refer to Figure 3, 4) PAGE ADDRESS REGISTE R The 3-bit page address register provides the page address to display data RAM (refer to Table 4). The microprocessor issues set page address instruction to change the page and to access another page. COLUMN ADDRESS COUNT ER The column address counter is a 6-bit pre-settable counter that provides column address to display data RAM (refer to Table 4). It is incremented by 1 automatically after execution of each read/write data instruction. The column address counter loops the values 0 to 127, and it is independent of page address register. The ADC pin is issued to change the relationship between RAM column address and display segment output. DISPLAY START LINE R EGISTER The display start line register stores the line address of display data RAM that corresponds to the first (normally the top) line (COM1) of liquid crystal display (LCD) panel. When displaying contents in display data RAM on the LCD panel, 6-bit data (DB[5:0]) of the set display start line is latched in display start line register. latched data are transferred to the line address counter just before COM1 is high, pre-setting the line address counter. The line counter is then incremented on the display latch clock signal once for every display line. It is used for vertical scrolling of the liquid crystal display screen.
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
LCD DRIVER LCD driver circuit has 192 outputs of 128 segment outputs, 64 common outputs for LCD driving. Each common output has a shift register. LCD driving output voltage is determined by the combination of display data and internal AC signal. Display Data 0 1 Display Off Common Output V1 V4 V5 V0 Segment Output V2 V3 V0 V5 V2 or V3
RESET CIRCUIT Reset function can initialize system by setting RESETB terminal at low level. When RESETB becomes low, following procedure occurs. * * Display start line: 0 (first) Display on/off: Off
While RESETB is in low level, no instruction except status read can be accepted. Reset status appears at DB4. Refers to read status of "instruction description" The conditions of power supply at initial power up are shown in table 5. Table 5. Power supply initial conditions. Item Reset time Rise time Symbol tRESETB tr Min 1.0 Typ Max 200 Unit s ns
tRESETB VDD
tr
0.7VDD 0.3VDD
RESETB
Figure 5. Reset timing
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
INSTRUCTION DESCRIPTION
Table 6. Instruction Table
Instruction RS Read display data Write display data 1 R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 Read Data Function Reads data (DB[0:7]) from display data RAM to the data bus. Writes data(DB[0:7]) into display data RAM. After writing instruction, column address is incremented by1 automatically. 0 0 0 Reads status BUSY 0: Ready 1: In operation ON/OFF 0: Display ON 1: Display OFF RESET 0: Normal 1: Reset Set column address Set display start line Set page address Display on/off 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 Column Address (0-63) Display Start Line (0-63) 1 1 1 1 1 Page (0-7) 1 0/1 Sets the column address at the column address counter Indicates the display data RAM displayed at the top of the screen. Sets the page address at the Page address register. Controls the display on or off. Internal status and display RAM data is not affected. 0: OFF 1: ON
1
0
Write Data
0 Status read
1
busy
0
on/ off
reset 0
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
DETAILED INSTRUCTION DESCRIPTIONS Read Display Data Reads 8-bit data in the display data RAM area specified by column address and page address. As the column address is incremented by 1 automatically after each read operation, the microprocessor can continue to read data of multiple words. RS 1 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Read Data
W rite Display Data Writes 8-bit data to the display data RAM As the column address is incremented by 1 automatically after each write operation, the microprocessor can continue to write data of multiple words. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 Write Data
Read Status Indicates the internal status conditions of the device to the microprocessor. RS 0 RW 1 DB7 Busy DB6 0 DB5 On/Off DB4 RESET DB3 0 DB2 0 DB1 0 DB0 0
Flag Busy On/Off RESET
Description The device is busy due to internal operation or reset. Any instruction is rejected until BUSY goes low. Indicates whether the display is on or off. When low, the display is on. When high, the display is off. This is the opposite of Display ON/OFF instruction. Indicates the initialization is in progress by RESETB signal. When low, the chip is in active. When high, the chip is being reset.
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
Set Page Address Sets the page address of display RAM from the microprocessor into the page address register. Along with column address register, Page address register assigns the address of the display RAM to be written to or read from display data. Changing the address doesn't affect the display status. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 1 DB3 1 DB2 X2 DB1 X1 DB0 X0
X2 0 0 : 1
X1 0 0 : 1
X0 0 1 : 1
Page 0 1 : 7
Set Column Address Sets the column address of display RAM from the microprocessor into the column address register. When the microprocessor reads or writes display data to or from display RAM, the address are automatically incremented. RS 0 RW 0 DB7 0 DB6 1 DB5 Y5 DB4 Y4 DB3 Y3 DB2 Y2 DB1 Y1 DB0 Y0
Y5 0 0 : 1 1
Y4 0 0 : 1 1
Y3 0 0 : 1 1
Y2 0 0 : 1 1
Y1 0 0 : 1 1
Y0 0 1 : 0 1
Column Address 0 1 : 62 63
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
Set Display Start Line Sets the line address of display RAM to determine the display start line. The display data on the specified line of the display RAM is displayed at the top row COM1 of LCD panel. It is followed by the higher number of lines in ascending order corresponding to the determined duty cycle. When this instruction changes the display start line address, the LCD panel can be scrolled. RS 0 RW 0 DB7 1 DB6 1 DB5 Z5 DB4 Z4 DB3 Z3 DB2 Z2 DB1 Z1 DB0 Z0
Z5 0 0 : 1 1
Z4 0 0 : 1 1
Z3 0 0 : 1 1
Z2 0 0 : 1 1
Z1 0 0 : 1 1
Z0 0 1 : 0 1
Line Address 0 1 : 62 63
Display ON / OFF Turns the display ON or OFF RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 1 DB2 1 DB1 1 DB0 D0
D0 = 1: Display ON D0 = 0: Display OFF
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S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
ELECTRICAL SPECIFICA TIONS
ABSOLUTE MAXIMUM RAT INGS Parameter Operating voltage Supply voltage Driver supply voltage Symbol VDD VEE VB VLCD Rating -0.3 - +7.0 VDD-19.0 - VDD+0.3 -0.3 - VDD+0.3 VEE-0.3 - VDD+0.3 Unit V Note
(1) (4) (1), (3) (2)
NOTES: 1. Based on Vss = 0V 2. VLCD = VDD - VEE 3. Applies to SHL, FS, PCLK2, CR, RESETB, ADC, CS1B, CS2B, E, RW, RS and DB0 - DB7. 4. Voltage level VDD V0 V1 V2 V3 V4 V5 VEE
TEMPERATURE CHARACTE RISTICS Parameter Operating temperature Storage temperature Symbol Topr Tstg Rating -30 - +85 -55 - +125 Unit C Note
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64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
ELECTRICAL CHARACTER ISTICS DC Characteristics (VDD = 4.5 to 5.5V, Ta = -30 to +85C)
Item Operating voltage Input high voltage Symbol VDD VIH1 VIH2 Input low voltage VIL1 VIL2 Output high voltage Output low voltage Input leakage current Tri-state leakage current Driver input leakage current Operating current VOH VOL ILKG ITSL IDLKG IDD1 IDD2 On resistance COM SEG Oscillation frequency RONC RONS fosc Ta = 25C, VDD = 5V Rf = 47k 2% Cf = 20pF 5% NOTES: 1. FS, CR, ADC, SHL, PCLK2, RESETB 2. CS1B, CS2B, E, RW, RS, DB0 - DB7 3. DB0 - DB7 4. Excepted DB0 - DB7 5. DB0 - DB7 at high impedance 6. V0, V1, V2, V3, V4, V5 7. C = 20pF, R = 47k, fose = 450kHz, DB0 - DB7 = VDD, output = No load 8. External clock = 430kHz, RAM access cycle = 1MHz 9. V0 = 5V, V1 = 3.2V, V2 = 1.4V, V3 = -8.4V, V4 = -10.2V, V5 = -12V, C1 - C64 10. V0 = 5V, V1 = 3.2V, V2 = 1.4V, V3 = -8.4V, V4 = -10.2V, V5 = -12V, S1 - S128 Condition IOH = -200uA IOL = 1.6mA VIN = VSS - VDD VIN = VSS - VDD VIN = VEE - VDD During display During access ILOAD = 0.1mA Min 4.5 0.7VDD 2.0 0 0 2.4 -1.0 -5.0 -10 315 Typ 450 Max 5.5 VDD VDD 0.3VDD 0.8 0.4 +1.0 +5.0 +10 0.8 1.0 1.5 7.5 585 kHz k mA A
(4) (5) (6) (7) (8) (9) (10)
Unit V
Note
(1) (2) (1) (2) (3)
23
S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
AC Characteristics (VDD = 4.5 to 5.5V, Ta = -30 to +85C) Mode Write mode E cycle time Item Symbol tcyc t r, t f tPWH tAS tAH tDS tDH tcyc t r, t f tPWH tAS tAH tDS tDH 20 Min 1000 450 140 10 200 10 1000 450 140 10 Typ Max 25 25 320 ns Unit ns
(refer to figure 6) E rise/fall time E pulse width high RW and RS setup time RW and RS hold time Data setup time Data hold time Read mode E cycle time
(refer to figure 7) E rise/fall time E pulse width high RW and RS setup time RW and RS hold time Data setup time Data hold time
RS
VIH1 VIL1 tAS VIL1 tPWH
tAH VIL1 tAH tf VIH1 VIL1 tDS VIH1 VIL1 tDH VIH1 VIL1
RW
E tf DB0 - DB7
VIH1 VIL1
VIL1
Valid Data tcyc
Figure 6. Write Mode Timing Diagram
24
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
RS
VIH1 VIL1 tAS VIH1 tPWH
tAH VIH1 tAH tf VIH1 VIL1 tD VOH1 VOL1 tDH Valid Data tcyc VOH1 VOL1
R/W
E tr DB0 - DB7
VIH1 VIL1
VIL1
Figure 7. Read Mode Timing Diagram
25
S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
APPLICATION DIAGRAM1 (ADC = H, SHL = H)
COM1 . . COM32
LCD panel (64 x 128)
S E G 1 S E G 2 .... SEG127 SEG128
C O M 33 . . C O M 64
S1 C32
. . . .
S2 . . . . S127
S128 C64 . . . . C33
S 6B 0 7 0 8
(Bottom view)
E R/W RS DB[0:7] RESETB CS1B CS1B CS2B VDD V0 V1 V2 V3 V4 V5 VEE
C1
VDD
12
V0 V1 V2
E R/W RS DB[0:7] RESETB
CS2B
V3 V4 V5
MPU
VEE
26
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
APPLICATION DIAGRAM2 (ADC = H, SHL = H)
COM1 C OM 33
. . .
LCD panel (6 4 x 1 2 8 )
S E G 1 SEG2 .... S E G 1 2 7 S E G 1 2 8
. . .
C OM 32
COM32
S128 C64
. . .
S127
.
.
.
S1
S1 C32
. . .
S 6 B 0 7 08
E R/W RS DB[0:7] RESETB
(T o p v i ew )
*CS2B
*CS1B CS2B
C33
C1 VDD
V0 V1 V2 V3 V4 V5 VEE
12
V0 V1 V2 V3 V4 V5
Note: When ADC=L, connects chip select pins (CS1B, CS2B) as follows.
E R/W RS DB[0:7] RESETB
*CS1B
MPU
VEE
-
CS1B (MPU) -> CS2B (S6B0708) CS2B (MPU) -> CS1B (S6B0708)
27
S6B0708 LCD
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX
APPLICATION DIAGRAM3 (ADC = H, SHL = H)
VDD V0 V1 MPU V2
*CS1B E R/W RS DB[0:7] RESETB *CS2B *CS1B
V3 V4 V5
12
E RW RS DB[0:7] RESETB
*CS2B
V0
V2 V1
V3
V4
V5
VEE
VEE
C1 . . . . C32
C 33 . . . . C 64
S6B 0 708
(B o ttom view)
S127 . . . S2 S1
S128
COM1 . . COM32
SEG1 SEG2 .... SEG127 SEG128
LCD panel (64 x 128)
COM33 . . COM64
Note: When ADC=L, connects chip select pins (CS1B, CS2B) as follows.
-
CS1B (MPU) -> CS2B (S6B0708) CS2B (MPU) -> CS1B (S6B0708)
28
64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX LCD S6B0708
APPLICATION DIAGRAM4 (ADC = H, SHL = H)
VDD V0 V1 MPU V2
*CS2B E R/W RS DB[0:7] RE SETB *CS2B *CS2B
V3 V4 V5
12
VEE
C33 . . . . C64
RS DB[0:7] RESETB
E RW
* CS 1B
V0
V2 V1
V3
V4
V EE V5
C1 . . . . C32
S 6 B 0708
(Top view)
S2 . . . S127 S128
S1
S E G 1 S E G 2 . .. . S E G 1 2 7 S E G 1 2 8
COM33 . . COM64
L CD panel (6 4 x 1 2 8 )
COM1 . . . C O M 32
29

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